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8237 dma controller - pdf download

8237A
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
(8237A-5)
Y
Enable/Disable Control of Individual
DMA Requests
Y
Directly Expandable to Any Number of
Channels
Y
Four Independent DMA Channels
Y
Y
Independent Autoinitialization of All
Channels
End of Process Input for Terminating
Transfers
Y
Software DMA Requests
Y
Independent Polarity Control for DREQ
and DACK Signals
Y
Available in EXPRESS
Ð Standard Temperature Range
Y
Available in 40-Lead Cerdip and Plastic
Packages
Y
Memory-to-Memory Transfers
Y
Memory Block Initialization
Y
Address Increment or Decrement
Y
High Performance: Transfers up to
1.6M Bytes/Second with 5 MHz 8237A-5
(See Packaging Spec, Order Ý231369)
The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer
information from the system memory. Memory-to-memory transfer capability is also provided. The 8237A
offers a wide variety of programmable control features to enhance data throughput and system optimization
and to allow dynamic reconfiguration under program control.
The 8237A is designed to be used in conjunction with an external 8-bit address latch. It contains four independent channels and may be expanded to any number of channels by cascading additional controller chips. The
three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can
be individually programmed to Autoinitialize to its original condition following an End of Process (EOP). Each
channel has a full 64K address and word count capability.
231466 – 2
Figure 2. Pin
Configuration
231466 – 1
Figure 1. Block Diagram
September 1993
Order Number: 231466-005
8237A
Table 1. Pin Description
Symbol
Type
VCC
VSS
2
Name and Function
POWER: a 5V supply.
GROUND: Ground.
CLK
I
CLOCK INPUT: Clock Input controls the internal operations of the
8237A and its rate of data transfers. The input may be driven at up
to 5 MHz for the 8237A-5.
CS
I
CHIP SELECT: Chip Select is an active low input used to select
the 8237A as an I/O device during the Idle cycle. This allows CPU
communication on the data bus.
RESET
I
RESET: Reset is an active high input which clears the Command,
Status, Request and Temporary registers. It also clears the first/
last flip/flop and sets the Mask register. Following a Reset the
device is in the Idle cycle.
READY
I
READY: Ready is an input used to extend the memory read and
write pulses from the 8237A to accommodate slow memories or
I/O peripheral devices. Ready must not make transitions during its
specified setup/hold time.
HLDA
I
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from
the CPU indicates that it has relinquished control of the system
busses.
DREQ0 –DREQ3
I
DMA REQUEST: The DMA Request lines are individual
asynchronous channel request inputs used by peripheral circuits to
obtain DMA service. In fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated
by activating the DREQ line of a channel. DACK will acknowledge
the recognition of DREQ signal. Polarity of DREQ is
programmable. Reset initializes these lines to active high. DREQ